Difference between revisions of "John Backes"

Revision as of 22:04, 5 April 2013

My research interests include logic synthesis, formal verification, technology mapping, and SAT-based algorithms.

Dissertation

title:	Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability
author:	John Backes
defended on:	March 1st, 2013.

Journal Papers

title:	The Synthesis of Cyclic Dependencies with Boolean Satisfiability
authors:	John Backes and Marc Riedel
will appear in:	ACM Transactions on Design Automation of Electronic Systems, 2012.

title:	The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability
authors:	John Backes, Brian Fett, and Marc Riedel
submitted to:	Journal on Satisfiability, Boolean Modeling and Computation, 2011.

title:	The Synthesis of Stochastic Circuits for Nanoscale Computation
authors:	Weikang Qian, John Backes, and Marc Riedel
appeared in:	International Journal of Nanotechnology and Molecular Computation, vol. 1, no. 4, pp. 39–57, 2010.

Conference Papers

title:	Using Cubes of Non-state Variables With Property Directed Reachability
authors:	John Backes and Marc Riedel
presented at:	Design Automation & Test in Europe, Grenoble, France, 2013.

title:	Resolution Proofs as a Data Structure For Logic Synthesis
authors:	John Backes and Marc Riedel
presented at:	The International Workshop on Logic Synthesis, La Jolla, CA, 2011.

title:	Reduction of Interpolants For Logic Synthesis
authors:	John Backes and Marc Riedel
presented at:	The International Conference on Computer-Aided Design, San Jose, CA, 2010.

title:	The Synthesis of Cyclic Dependencies with Craig Interpolation
authors:	John Backes and Marc Riedel
presented at:	The International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

title:	The Analysis of Cyclic Circuits with Boolean Satisfiability
authors:	John Backes, Brian Fett, and Marc Riedel
presented at:	The International Conference on Computer-Aided Design, San Jose, CA, 2008.

@@ Line 6: / Line 6: @@
 == John's Papers ==
+'''Dissertation'''
+{|
+| rowspan=2 |
+{| style="background:#F0E68C"
+|- valign=top
+|  width="100" | '''title''':
+|  width="500" | [[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf‎‎ ‎‎‎ | Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability]]
+|-
+| '''author''':
+| [[John Backes]]
+|-
+| '''defended&nbsp;on''':
+|  March 1st, 2013.
+|}
+| align=center width="70" |
+<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/9/96/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
+<br>[[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf‎‎‎  | Paper]]
+| align=center width="70" |
+<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
+<br> [http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx Slides]
+|}
 '''Journal Papers'''