John Backes

Email: <img alt="BackesEmail.gif" src="/wiki/images/f/f1/BackesEmail.gif" decoding="async" width="155" height="15" data-file-width="155" data-file-height="15" />
Phone: (952) 239-7828

About John

My research interests include Logic Synthesis, Formal Verification, Technology Mapping, and SAT-Based Algorithms.

Journal Papers

title:	The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability
authors:	John Backes, Brian Fett and Marc Riedel
submitted to:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010

title:	The Synthesis of Stochastic Circuits for Nanoscale Computation
authors:	Weikang Qian, John Backes, and Marc Riedel
presented at:	International Journal of Nanotechnology and Molecular Computation, 2010.

Conference Papers

title:	Reduction of Interpolants For Logic Synthesis
authors:	John Backes and Marc Riedel
presented at:	The International Conference on Computer-Aided Design, San Jose, CA, 2010.
presented at:	International Workshop on Logic and Synthesis, Irvine, CA, 2010.

title:	The Synthesis of Cyclic Dependencies with Craig Interpolation
authors:	John Backes and Marc Riedel
presented at:	International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

title:	The Analysis of Cyclic Circuits with Boolean Satisfiability
authors:	John Backes, Brian Fett and Marc Riedel
presented at:	The International Conference on Computer-Aided Design, San Jose, CA, 2008.