EE2301

From The Circuits and Biology Lab at UMN
Revision as of 21:38, 6 September 2007 by Wikisysop (talk | contribs) (New page: == Organization, Spring 2007 == === People === * '''Instructor''': Prof. Marc Riedel ([mailto:mriedel@umn.edu mriedel@umn.edu]) * '''Course TA''': Jie Chen ([mailto:chen0868@umn.edu ...)
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Organization, Spring 2007

People

Lecture

  • Lecture: Tu. & Th. 9:45am - 11:00am, Fraser Hall, room 101

Discussions

  • Discussion (EE301 Section 1): Tues. 11:15am - 12:05am, EE/CSi 4-138
  • Discussion (EE301 Section 4): Tues. 1:25pm - 2:15pm, EE/Csi 4-138

Lab

  • Lab (Section 3): Wed. 01:25pm - 03:20pm, EE/CSi 2-178
  • Lab (Section 4): Thur. 03:35pm - 05:30pm, EE/CSi 2-178
  • Lab (Section 5): Thur. 11:15am - 01:10pm, EE/CSi 2-178
  • Lab (Section 6): Thur. 01:25pm - 03:20pm, EE/CSi 2-178

Office Hours

  • Marc Riedel: Wed. 1:00pm - 3:00pm, EE/CSi 4-167 (or by appointment)
  • Jie Chen: Mon. 1:00 - 2:00pm, EE/CSi 6-188

Text & Manuals

Text: Charles H. Roth, Jr., Fundamentals of Logic Design, 5th ed.

Lab Manual: The parts you need for the laboratory are available as a laboratory kit in the bookstore. The kit is a combination of the parts for the EE 2301 lab and the parts for the 2002/2006/3101/3102 labs.

Grading

  • Homework: 20%
    • 8 homeworks, weighted equally (all questions, all parts)
  • Laboratory: 20%
    • 8 experiments, weighted equally
    • For each experiment:
      • Attendance: 10%
      • Prelab: 10%
      • Report: 60%
      • Evaluation of Lab Work: 20%
  • Midterm Exam 1 (Thurs. March 8, in class): 20%
  • Midterm Exam 2 (Thurs., April 19, in class): 20%
  • Final Exam (Sat., May 12, 8am - 10am, Frazer Hall, 101): 20%

Policies

  • Exams are closed-book (no notes allowed) that will take place in class.
  • Calculators, phones, computers, or any other electronic devices may not be used in the exams.
  • There will be no make-up exams except for verifiable illness or incapacity, approved by the Institute.
  • An incomplete grade will only be given when all but a small portion of the coursework is complete and the student is unable to finish because of verifiable illness or incapcity, approved by the Institute. See University Senate Grading Policy.
  • All work submitted for the course must be the sole work of the student. Any student who copies from another or cheats in any manner will receive a 0 for that assignment/exam with the possibility of more severe punishment, such as receiving an 'F' for the course or expulsion. See Univesity's Student Conduct Policies. Also, see the Institute of Technology¿s policies regarding dishonest and disruptive behavior.

Topics

  • Introduction to Digital Logic (4 weeks)
    • Gates
    • Combinational Circuits
    • Number Systems
    • Boolean Expressions
    • Representation of Boolean Functions
      • Truth Tables
      • Sum-of-Products / Product-of-Sums
      • "Don't Cares"
      • Binary Decision Diagrams
  • Logic Minimization (3 weeks)
    • Two-level
      • Karnaugh maps
      • Prime implicants
      • Espresso
    • Multiple-level
      • Decomposition, Factoring, Substitution

Midterm Exam 1: Thurs. March 8, in class

  • Combinational Circuit Design (3 weeks)
    • Combinational Logic Modules (Adders, Multiplexers, Decoders, etc.)
    • Programmable Logic
    • Introduction to VHDL (I)
  • Introduction to Sequential Circuits (2 weeks)
    • Latches & Flip-flops
      • S-R and D Latches
      • S-R, J-K, D, and T Flip-Flops
    • State Graphs and Tables

Midterm Exam 2: Tue., April 17, in class

  • Sequential Circuit Design (3 weeks)
    • Sequential Logic Modules (Counters, Registers, etc.)
    • State Assignments
      • State Equivalence
      • Reduction
      • Synchronous State-Machine Design
    • Introduction to VHDL (II)

Final Exam: Sat., May 12

Homeworks and Exams

Lecture Notes and References

Labs

Experiments

Lab Equipment